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22.4 Register Map
The offset register address is relative to the registers base address.
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
Name
PCNTn_CTRL
PCNTn_CMD
PCNTn_STATUS
PCNTn_CNT
PCNTn_TOP
PCNTn_TOPB
PCNTn_IF
PCNTn_IFS
PCNTn_IFC
PCNTn_IEN
PCNTn_ROUTE
PCNTn_FREEZE
PCNTn_SYNCBUSY
Type
RW
W1
R
R
R
RW
R
W1
W1
RW
RW
RW
R
Description
Control Register
Command Register
Status Register
Counter Value Register
Top Value Register
Top Value Buffer Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Interrupt Enable Register
I/O Routing Register
Freeze Register
Synchronization Busy Register
22.5 Register Description
22.5.1 PCNTn_CTRL - Control Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
Offset
0x000
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
5
RSTEN
0
RW
Enable PCNT Clock Domain Reset
The PCNT clock domain is asynchronously held in reset when this bit is set. The reset is synchronously released two PCNT clock
edges after this bit is cleared. If external clock used the reset should be performed by setting and clearing the bit without pending
for SYNCBUSY bit.
4
FILT
0
RW
Enable Digital Pulse Width Filter
The filter passes all high and low periods that are at least 5 clock cycles long. This filter is only available in OVSSINGLE mode.
3
EDGE
0
RW
Edge Select
Determines the polarity of the incoming edges. This bit should be written when PCNT is in DISABLE mode, otherwise the behavior
is unpredictable. This bit is ignored in EXTCLKSINGLE mode.
Value
0
1
Mode
POS
NEG
Description
Positive edges on the PCNTn_S0IN inputs are counted in OVSSINGLE mode.
Negative edges on the PCNTn_S0IN inputs are counted in OVSSINGLE mode, and
the counter direction is inverted in EXTCLKQUAD mode.
2011-04-12 - d0001_Rev1.10
315
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